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power management & drives preliminary datasheet v1.2 ICB2FL02G smart ballast control ic for fluorescent lamp ballasts published by in fineon technologies ag http://www.infineon.com never stop thinking
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 2 from 55 ICB2FL02G v1.2 ICB2FL02G revision history preliminary datasheet ICB2FL02G actual release: v1.2 date: 08.02.2010 previous release: v1.1 - 17.03.2009 page of actual rel. page of prev. rel. subjects changed since last release 3 3 updated product highlights; updated description 14 14 text update: r41, r42 and r43 ? r41, r42,r43 and r44 23 23 figure 17 update 25 25 text update: r41, r42 and r43 ? r41, r42,r43 and r44 26 26 text update: r41, r42 and r43 ? r41, r42,r43 and r44 29 29 chapter 2.6.2 text and figure update 39 39 figure 37 additional ex planation in the diagram 40 40 update protection function matrix open filament ls ? open filament hs @ lvs1 47 47 chapter 5.3.3.1 footnote update 51 51 enlarged tolerance for customer test mode 53 53 chapter 6.2: bom update deleted partnumbers of mosfets for questions on technology, delivery and prices please contact the infineon technologies offices in germany or t he infineon technologies companies and representatives worldwide: see the address list on the last page or our webpage at http://www.infineon.com published by infineon technologies ag 81726 munich, germany ? 2007 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non- infringement of intellectual property rights of any third party. information for further information on technology, deliver y terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon techno logies, if a failure of such components can reasonably be expected to cause the failure of th at life-support device or system or to affect the safety or effectiven ess of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the health of the user or other persons may be endangered.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 3 from 55 ICB2FL02G v1.2 2nd generation fl-controller for fluorescent lamp ballasts product highlights lowest count of external components 900v-half-bridge driver with coreless transformer technology supports customer in-circuit test mode for reduced tester time supports multi-lamp designs integrated digital timers up to 40 seconds numerous monitoring and protection features for highest reliability very high accuracy of frequencies and timers over the whole temperature range very low standby losses special detection thresholds for dimming applications features pfc discontinuous mode pfc for load range 0 to 100% integrated digital compensation of pfc control loop improved compensation for low thd of ac input current also in dcm operation adjustable pfc current limitation features lamp ballast inverter adjustable detection of overl oad and rectifier effect (eol) detection of capacitive load operation improved ignition control allows operation close to the magnetic saturation of the lamp inductors restart with skipped preheating at short interrupt ions of line voltage (for emergency lighting) parameters adjustable by resistors only pb-free lead plating; rohs compliant figure 1 typical application circuit of ballast for a single fluorescent lamp description the fl-controller ICB2FL02G is designed to control fluorescent lamp ballast including a discontinuous mode power factor correction (pfc), a lamp inverter control and a high voltage level shift half-bridge driver with special detection thresholds for dimming applications. the control concept covers requirements for t5 la mp ballasts for single and multi-lamp designs. ICB2FL02G is based on the 2 nd generation fl-controller technology, is easy to use and simply to design in. therefore a basis for a cost effective solution for fluorescent lamp ballasts of high reliability. figure 1 shows a typical application circuit of ballast for a single fluorescent t8 lamp with current mode preheating.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 4 from 55 ICB2FL02G v1.2 table of contents 1 pin configuration and descr iption.............................................................................................. .6 1.1 pin config uration.............................................................................................................. ......... 6 1.2 pin descr iption ................................................................................................................ .......... 6 2 functional d escripti on ......................................................................................................... ....... 11 2.1 typical application circutry................................................................................................... .. 11 2.2 normal st art up ................................................................................................................ ...... 12 2.2.1 operating levels from uvlo to so ft start............................................................................ 13 2.2.2 operating levels from soft start to run mo de ..................................................................... 15 2.3 filament detection during start up and run mode ................................................................ 17 2.3.1 start up with br oken low side filament............................................................................... 17 2.3.2 low side filament de tection during run mo de.................................................................... 18 2.3.3 start up with br oken high side filament .............................................................................. 19 2.4 pfc pre co nverter.............................................................................................................. .... 20 2.4.1 discontinuous conduction and crit ical conduction mode operat ion ................................... 20 2.4.2 pfc bus vo ltage sensing.................................................................................................. ... 21 2.4.2.1 bus over voltage and pfc open loop ................................................................... 21 2.4.2.2 bus voltage 95% and 75% sens ing......................................................................... 21 2.4.3 pfc structur e of mix ed signal............................................................................................ .. 22 2.4.4 thd correcti on via zcd signal ............................................................................................ 23 2.4.5 optional thd correction dedi cated for dcm operation....................................................... 24 2.5 detection of end-of-life and rectifie r effect........................................................................... 25 2.5.1 detection of end of life 1 (eol1) ? lam p overvoltage........................................................ 25 2.5.2 detection of end of life 2 (eol2) ? rect ifier effect.............................................................. 26 2.6 detection of capacitive load .................................................................................................. 2 7 2.6.1 capacitive load 2 (o ver current / operati on below res onance) ........................................ 28 2.6.2 adjustable self adapting de ad time ..................................................................................... 29 2.7 emergency li ghting ............................................................................................................. ... 30 2.7.1 short term pfc bus under voltage..................................................................................... 31 2.7.2 long term pfc bu s under vo ltage ..................................................................................... 32 2.8 built in customer te st mode oper ation.................................................................................. 33 2.8.1 pre heati ng test mode .................................................................................................... ..... 33 2.8.1.1 skip the pre heating phase ? set rtph pi n to gnd.............................................. 33 2.8.1.2 ic remains in pre heating p hase ............................................................................. 34 2.8.2 deactivation of the filament de tection ................................................................................. 35 2.8.3 built in customer test mode (clock ac celeration) ............................................................... 36 2.8.3.1 enabling of the clo ck acceleration........................................................................... 36 2.8.3.2 starting the chip with accelerated clock.................................................................. 36 3 state di agram .................................................................................................................. ............. 37 3.1 features during differ ent operatin g modes ............................................................................. 37 3.2 operating flow of the start up procedure into the run mode............................................... 38 3.3 auto restart and latched fault condit ion m ode.................................................................... 39 4 protection func tions matrix.................................................................................................... .... 40 5 electrical char acteristics ..................................................................................................... ....... 41
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 5 from 55 ICB2FL02G v1.2 5.1 absolute maxi mum ratings .................................................................................................... 41 5.2 operati ng range................................................................................................................ ..... 43 5.3 characteristics ................................................................................................................ ........ 44 5.3.1 power s upply sect ion ..................................................................................................... ...... 44 5.3.2 pfc section .............................................................................................................. ............ 45 5.3.2.1 pfc current sens e (pfccs)................................................................................... 45 5.3.2.2 pfc zero current de tection (p fczcd)................................................................... 45 5.3.2.3 pfc bus voltage se nse (pfc vs) ........................................................................... 45 5.3.2.4 pfc pwm gener ation.............................................................................................. 46 5.3.2.5 pfc gate driv e (pfcgd ) ........................................................................................ 46 5.3.2.6 auxiliary (aux) ......................................................................................................... 46 5.3.3 inverter section ......................................................................................................... ............ 47 5.3.3.1 low side current sense (lscs).............................................................................. 47 5.3.3.2 low side gate dr ive (lsgd) ................................................................................... 48 5.3.3.3 inverter control run (rfrun) ................................................................................. 49 5.3.3.4 inverter control preheat ing (rfph, rtph) ............................................................. 49 5.3.3.5 restart after lamp removal (res).......................................................................... 50 5.3.3.6 lamp voltage sense (lvs1, l vs2) ......................................................................... 50 5.3.3.7 high side gate dr ive (hsgd) .................................................................................. 51 5.3.3.8 timer sect ion ........................................................................................................... 51 5.3.3.9 built in customer test mode .................................................................................... 51 6 application example ............................................................................................................ ........ 52 6.1 schematic ballast 54 w t5 singl e lamp................................................................................. 52 6.2 bill of ma terial............................................................................................................... ........... 53 6.3 multi lamp ballast topologies ................................................................................................ 54 7 package ou tlines ............................................................................................................... .......... 55
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 6 from 55 ICB2FL02G v1.2 1 pin configuration and description 1.1 pin configuration pin symbol function 1 lscs low side current sense (inverter) 2 lsgd low side gate drive (inverter) 3 v cc supply voltage 4 gnd low side ground 5 pfcgd pfc gate drive 6 pfccs pfc current sense 7 pfczcd pfc zero current detector 8 pfcvs pfc voltage sense 9 rfrun set r for run frequency 10 rfph set r for preheat frequency 11 rtph set r for preheating time 12 res restart after lamp removal 13 lvs1 lamp voltage sense 1 14 lvs2 lamp voltage sense 2 15 aux auxiliary output 16 creepage distance 17 hsgnd high side ground 18 hsvcc high side supply voltage 19 hsgd high side gate drive (inverter) 20 not connected hsvcc hsgnd rfph res lvs1 pg-dso-19-1 (300mil) lvs2 rfrun pfcvs pfczcd gnd hsgd lsgd pfcgd lscs pfccs vcc rtph n.c. 10 9 8 7 4 2 5 1 6 3 11 12 13 14 17 19 16 20 15 18 aux figure 2 package pg-dso-19-1 1.2 pin description lscs (low-side current sense, pin 1) this pin is directly connected to the shunt resistor which is located between the source terminal of the low-side mosfet of the inverter and ground. internal clamping structures and filtering measures allow for sensing the source current of the low side inverter mosfet without additional filter components. there is a first threshold of 0.8v. if this threshold is exceeded for longer than 500ns during preheat or run mode, an inverter over current is detected and causes a latched shut down of the ic. the ignition control is activated if the sensed slope at the lscs pin reaches typically 205 mv/s 25 mv/s and exceeds the 0.8v threshold. this stops the decreasing of the frequency and waits for ignition. the ignition control is now continuously monitored by the lscs pin. the ignition control is designed to handle a choke operation in saturation while ignition in order to reduce the choke size. if the sensed current signal exceeds a second threshold of 1.6v for longer than 500ns during start-up, soft start, ignition mode and pre-run, the ic changes over into a latched shut down. there are further thresholds active at this pin during run mode that detects a capacitive mode operation. a threshold of -50mv senses the current before the high-side mosfet is turned on. a voltage level below of this threshold indicates a faulty operation (capload 2). finally a second threshold at 2.0 v senses even short overcurrent during turn-on of the high-side mosfet such as they are typical for reverse recovery currents of a diode (capload 2). if one of these comparator thresholds indicate wrong operating conditions for longer than 620s (capload 2) in run mode, the ic turns off the gates and changes into fault mode due to detected capacitive mode operation (non-zero voltage switching). the threshold of -50mv is also used to adjust the dead time between turn-off and turn-on of the half-bridge drivers in a range of 1.05s to 2.0s during all operating modes.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 7 of 55 ICB2FL02G v1.2 lsgd (low-side gate drive, pin 2) the gate of the low-side mosfet in a half- bridge inverter topology is controlled by this pin. there is an active l-level during uvlo (under voltage lockout) and a limitation of the max h- level at 11.0 v during normal operation. in order to turn-on the mosfet softly (with a reduced di drain /dt); the gate voltage rises within 220ns typically from l-level to h-level. the fall time of the gate voltage is less than 50ns in order to turn off quickly. this measure produces different switching speeds during turn-on and turn-off as it is usually achieved with a diode parallel to a resistor in the gate drive loop. it is recommended to use a resistor of typically 10 ? between drive pin and gate in order to avoid oscillations and in order to shift the power dissipation of discharging the gate capacitance into this resistor. the dead time between lsgd signal and hsgd signal is self adapting between 1.05s and 2.0s. vcc (supply voltage, pin 3) this pin provides the power supply of the ground related section of the ic. there is a turn-on threshold at 14.1v and an uvlo threshold at 10.6v. upper supply voltage level is 17.5v. there is an internal zener diode clamping v cc at 16.3v (at i vcc =2ma typically). the maximum zener current is internally limited to 5ma. for higher current levels an external zener diode is required. current consumption during uvlo and during fault mode is less than 170a. a ceramic capacitor close to the supply and gnd pin is required in order to act as a low-impedance power source for gate drive and logic signal currents. in order to use a skipped preheating after short interruptions of mains supply it is necessa ry to feed the start-up current (160a) from the bus voltage. note: for external v cc supply see notes in flowchart chapter 3.3. gnd (ground, pin 4) this pin is connected to ground and represents the ground level of the ic for supply voltage, gate drive and sense signals. pfcgd (pfc gate drive, pin 5) the gate of the mosfet in the pfc preconverter designed in boost topology is controlled by this pin. there is an active l-level during uvlo and a limitation of the max h-level at 11.0 v during normal operation. in order to turn-on the mosfet softly (with a reduced di drain /dt), the gate drive voltage rises within 220ns from l-level to h-level. the fall time of the gate voltage is less than 50ns in order to turn off quickly. a resistor of typically 10 ? between drive pin and gate in order to avoid oscillations and in order to shift the power dissipation of discharging the gate capacitance into this resistor is recommended. the pfc section of the ic controls a boost converter as a pfc preconverter in discontinuous conduction mode (dcm). typically the control starts with gate drive pulses with a fixed on-time of typically 4.0s at v acin = 230v increasing up to 22.7s and with an off-time of 47s. as soon as sufficient zero current detector (zcd) signals are available, the operation mode changes from a fixed frequent operation to an operation with variable frequency. the pfc works in a critical conduction mode operation (critcm) when rated and / or medium load conditions are present. that means triangular shaped currents in the boost converter choke without gaps and variable operating frequency. during low load (detected by an internal compensator) we get an operation with discontinuous conduction mode (dcm) that means triangular shaped currents in the boost converter choke with gaps when reaching the zero current level and variable operating frequency in order to avoid steps in the consumed line current. pfccs (pfc current sense, pin 6) the voltage drop across a shunt resistor located between source of the pfc mosfet and gnd is sensed with this pin. if the level exceeds a threshold of 1.0 v for longer than 200ns the pfc gate drive is turned off as long as the zero current detector (zcd) enables a new cycle. if there is no zcd signal available within 52s after turn-off of the pfc gate drive, a new cycle is initiated from an internal start-up timer. pfczcd (pfc zero current detector, pin 7) this pin senses the point of time when the current through boost inductor becomes zero during off-time of the pfc mosfet in order to initiate a new cycle. the moment of interest appears when the voltage of the separate zcd winding changes from positive to negative level which represents a voltage of zero at the inductor windings and therefore the end of current flow from lower input voltage level to higher output voltage level. there is a threshold with hysteresis, for increasing level 1.5v, for decreasing level 0.5v, which detects the change of inductor voltage.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 8 of 55 ICB2FL02G v1.2 a resistor, connected between zcd winding and pin 7, limits the sink and source current of the sense pin when the voltage of the zcd winding exceeds the internal clamping levels (6.3v and -2.9v typically @ 5ma) of the ic. if the sensed voltage level of the zcd winding is not sufficient (e.g. during start-up), an internal start-up timer will initia te a new cycle every 52s after turn-off of the pfc gate drive. the source current out of this pin during the on-time of the pfc-mosfet indicates the voltage level of the ac supply voltage. during low input voltage levels the on-time of the pfc-mosfet is enlarged in order to minimize gaps in the line current during zero crossing of the line voltage and improve the thd (total harmonic distortion) of the line cu rrent. an optimization of the thd is possible by trimming of the resistor between this pin and the zcd-winding. pfcvs (pfc voltage sense, pin 8) the intermediate circuit voltage (bus voltage) at the smoothing capacitor is sensed by a resistive divider at this pin. the internal reference voltage for rated bus voltage is 2.5v. there are further thresholds at 0. 3125v (12.5% of rated bus voltage) for the detection of open control loop and at 1.875v (75% of rated bus voltage) for the detection of an under voltage and at 2.725v (109% of rated bus voltage) for the detection of an overvoltage. the overvoltage threshold operates with a hysteresis of 100mv (4% of rated bus voltage). for the detection of a successful start-up the bus voltage is sensed at 95% (2.375v). it is recommended to use a small capacitor between this pin and gnd as a spike suppression filter. in run mode, a pfc overvoltage stops the pfc gate drive within 5s. as soon as the bus voltage is less than 105% of rated level, the gate drives are enabled again. if the overvoltage lasts for longer than 625ms, an inverter overvoltage is detected and turns off the inverter the gate drives also. this causes a power down and a power up when v bus <109%. a bus under- (v bus >75%) or inverter overvoltage during run mode is handled as fault u. in this situation the ic changes into power down mode and generates a delay of 100ms by an internal timer. then start-up conditions are checked and if valid, a further start-up is initiated. if start-up conditions are not valid, a further delay of 100ms is generated. this procedure is repeated maximum seven times. if a start-up is successful within these seven cycles, the situation is interpreted as a short interruption of mains supply and the preheating is skipped. any further start-up attempt is initiated including the preheating. rfrun (set r for run frequency, pin 9) a resistor from this pin to ground sets the operating frequency of the inverter during run mode. typical run frequency range is 20 khz to 120 khz. the set resistor r_rfrun can be calculated based on the run frequency f run according to the equation: run frun f hz r ? = 8 10 5 rfph (set r for preheat frequency, pin 10) a resistor from this pin to ground sets together with the resistor at pin 9 the operating frequency of the inverter during preheat mode. typical preheat frequency range is run frequency (as a minimum) to 150 khz. the set resistor r_rfph can be calculated based on the preheat frequency f ph and the resistor r rfrun according to the equation: 1 10 5 8 ? ? ? = hz r f r r rfrun ph rfrun rfph rtph (set r for preheating time, pin 11) a resistor from this pin to ground sets the preheating time of the inverter during preheat mode. a set resistor range from zero to 25k ? corresponds to a range of preheating time from zero to 2500ms subdivided in 127 steps. = k ms t r eheating rtph 100 pr res (restart, pin 12) a source current out of this pin via resistor and filament to ground monitors the existence of the low-side filament of the fluorescent lamp for restart after lamp removal. a capacitor from this pin directly to ground eliminates a superimposed ac voltage that is generated as a voltage drop across the low-side filament. with a second sense resistor the filament of a paralleled lamp can be included into the lamp removal sense. note: during start up, the chip supply voltage vcc has to be below 14.1v before v res reaches the filament detection level.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 9 of 55 ICB2FL02G v1.2 during typical start-up with connected filaments of the lamp a current source i res3 (-21.3 a) is active as long as v cc > 10.6v and v res < v res1 (1.6v). an open low-side filament is detected, when v res > v res1 . such a condition will prevent the start-up of the ic. in addition the comparator threshold is set to v res2 (1.3v) and the current source changes to i res4 (-17.7 a). now the system is waiting for a voltage level lower than v res2 at the res pin that indicates a connected low-side filament, which will enable the start-up of the ic. an open high-side filament is detected when there is no sink current i lvssink (>18 a) into both of the lvs pins before the v cc start-up threshold is reached. under these conditions the current source at the res pin is i res1 (-42.6 a) as long as v cc > 10.6v and v res < v res1 (1.6v) and the current source is i res2 (-35.4 a) when the threshold has changed to v res2 (1.3v). in this way the detection of the high-side filament is mirrored to the levels on the res pin. there is a further threshold of 3.2v active at the res pin during run mode. if the voltage level rises above this threshold for longer than 620s, the ic changes over into latched fault mode. in any case of fault detection with different reaction times the ic turns-off the gate drives and changes into power down mode with a current consumption of 170 a max. an internal timer generates a delay time of 200 ms, before start-up conditions are checked again. as soon as start-up conditions are valid, a second start- up attempt is initiated. if this second attempt fails, the ic remains in latched fault mode until a reset is generated by uvlo or lamp removal. the res pin can be deactivated via set the pin to gnd (durable). lvs1 (lamp voltage sense 1, pin 13) before start-up this pin senses a current fed from the rectified line voltage via resistors through the high-side filaments of the lamp for the detection of an inserted lamp. the sensed current fed into the lvs pin has to exceed 12 a typically at a voltage level of 6.0 v at the lvs pin. the reaction on the high side filament detection is mirrored to the res pin (see pin 12). in addition the detection of available mains supply after an interruption is sensed by this pin. together with pin lvs2 and pin res the ic can monitor the lamp removal of totally four lamps. if the functionality of this pin is not required, e.g. for single lamp designs, it can be disabled by connecting this pin to ground. during run mode the lamp voltage is monitored with this pin by sensing a current proportional to the lamp voltage via resistors. an overload is indicated by an excessive lamp voltage. if the peak to peak lamp voltage effects a peak to peak current above a threshold of 210a pp for longer than 620s, a fault eol1 (end-of-life) is assumed. if the dc current at the lvs pin exceeds a threshold of 42a for longer than 2500ms, a fault eol2 (rectifier effect) is assumed. the levels of ac sense current and dc sense current can be set separately by external rc network. note, in case of a deactivation of the lvs1/2 pin, a reactivation starts, when the voltage at lvs1/2 pin exceeds v lvsenable1 in run mode. lvs2 (lamp voltage sense 2, pin 14) lvs2 has the same functionality as pin lvs1 for monitoring in parallel an additional lamp circuitry. aux (auxiliary output, pin 15) this pin provides a control current for a npn bipolar transistor during dcm operating mode of the pfc section. there is a source current of -450a plus the current which is fed into pin pfczcd from the detector winding available only during the enlarged off-time. that differ the discontinuous conduction mode (dcm) from the critical conduction mode (critcm). with this transistor a resistor for damping oscillations can be switched to the zcd winding in order to minimize the line current harmonics during dcm operating mode. if this function is not used, this pin has to be not connected. pin 16 not existing pin 16 does not exist, in order to provide a wider creepage distance to the high-side gate driver. please pay attention to relevant standards. hsgnd (high-side ground, pin 17) this pin is connected to the source terminal of the high-side mosfet which is also the node of high-side and low-side mosfet. this pin represents the floating ground level of the high- side driver and the high-side supply.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 10 of 55 ICB2FL02G v1.2 hsvcc (high-side supply voltage, pin 18) this pin provides the power supply of the high- side ground related section of the ic. an external capacitor between pin 17 and pin 18 acts like a floating battery which has to be recharged cycle by cycle via high voltage diode from low-side supply voltage during on-time of the low-side mosfet. there is an uvlo threshold with hysteresis that enables high-side section at 10.1v and disables it at 8.4v. hsgd (high-side gate drive, pin 19) the gate of the high-side mosfet in a half- bridge inverter topology is controlled by this pin. there is an active l-level during uvlo and a limitation of the max h-level at 11.0 v during normal operation. the switching characteristics are the same as described for lsgd (pin 2). it is recommended to use a resistor of about 10 ? between drive pin and gate in order to avoid oscillations and in order to shift the power dissipation of discharging the gate capacitance into this resistor. the dead time between lsgd signal and hsgd signal is self adapting between 1.05s and 2.0s (typically). not connected (pin 20) this pin is internally not connected.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 11 of 55 ICB2FL02G v1.2 functional description 2 functional description 2.1 typical application circutry pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs 90 ... 270 vac c2 c10 c11 c1 c16 c14 c13 c12 c15 c17 c19 c24 c40 r36 r1 r2 dr12 r13 r14 r15 r16 r20 r18 r21r22r23 r11 r12 r34 r35 r41 r42 r43 r26 r27 r30 r25 r45 d1...4 d9 d8 d5 d7 d6 l101 l1 l2 q1 q2 q3 r44 figure 3 application circuit of ballast for a single fluorescent lamp (fl) the schematic in figure 3 shows a typical application for a t5 single fluorescence lamp. it is designed for universal input voltage from 90 v ac until 270 v ac . the following chapters are explaining the components and referring to this schematic.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 12 of 55 ICB2FL02G v1.2 functional description 2.2 normal start up this chapter describes the basic operation flow (8 phases) from the uvlo (under voltage lock out) into run mode without any error detection. for detailed infromation see the following chapters 2.2.1 and 2.2.2. figure 4 shows the 8 different phases during a typical start form uvlo (phase 1 figure 4) to run mode (phase 8 figure 4) into normal operation (no failure detected). in case the ac line input is switched on, the v cc voltage rises to the uvlo threshold v cc = 10.6 v (no ic activities during uvlo). if v cc exceeds the first threshold of v cc = 10.6 v, the ic starts the first level of detection activity, the high and low side filament detection during the start up hysteresis (phase 2 figure 4). mode / time frequency / lamp voltage 42 khz soft start preheating ignition pre-run run mode into normal operation 100 khz 135 khz frequency lamp voltage 0 khz v cc = 17.5 v v cc = 14.1 v v cc = 10.6 v monitoring uvlo chip supply voltage v cc chip supply voltage v cc = 0 v rated bus voltage v bus mode / time mode / time 100 % rated bus voltage start up 1 2 3 5 4 6 7 8 95 % 30 % 60ms 35ms 80ms 11ms 0 - 2500ms 40 - 237ms 625ms 50 khz figure 4 typical start up procedure in run mode (in normal operation) followed by the end of the start up hysteresis (phase 2 figure 4) v cc > 14.1 v and before phase 3 is active, a second level of detection activity senses for 130 s (propagation delay of the ic) whether the rated bus voltage is below 12.5 % or above 105 %. if the previous bus voltage conditions are fulfilled and the filaments are detected, the ic starts the operation with an inte rnally fixed startup frequency of typically 135 khz (all gates are active). in case the bus voltage reaches a level of 95% of the rated bus voltage within latest 80ms (phase 3 figure 4), the ic enters the soft start. during the soft start (phase 4 figure 4), the start up frequency shifts from 135 khz down to the set preheating frequency (chapter 2.2.2). in the soft start phase, the lamp voltage ri ses and the chip supply voltage reaches its working level from 10.6 v < v cc < 17.5 v. after finish the soft start, the ic enters the preheating mode (phase 5 figure 4) for preheating the filam ents (adjustable time) in order to extend the life cycle of the fl filaments. by finishing the preheating, the controlle r starts the ignition (phase 6 figure 4). during the ignition phase, the frequency decreases from the se t preheating frequency down to the set operation frequency (adjustable see chapter 2.2.2). if the ignition is successf ul, the ic enters the pre ? run mode (phase 7 figure 4).
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 13 of 55 ICB2FL02G v1.2 functional description this mode is in order to prevent a malfunction of the ic due to an instable system e.g. the lamp parameters are not in a steady state condition. after finish the 625 ms pre run phase, the ic switches over to the run mode (phase 8 figure 4) with a complete monitoring. 2.2.1 operating levels from uvlo to soft start this chapter describes the operating flow from phase 1 (uvlo) until phase 4 (soft start) in detail. the control of the ballast is able to start the operation with in less than 100 ms (ic in active mode). this is achieved by a small start up capacitor (about 1f c12 and c13 ? fed by start up resistors r11 and r12 in figure 3) and the low current consumption during the uvlo (i vcc = 130 a ? phase 1 figure 5) and start up hysteresis (i vcc = 160 a ? defines the start up resi stors ? phase 2 figure 5) phases. the chip supply stage of the ic is protected ag ainst over voltage via an internal zener clamping network which clamps the voltage at 16.3 v and allo ws a current of 2.5 ma. for clamping currents above 2.5 ma, an external zener diode (d9 figure 3) is required. 1 v cc 16.0 v 14.1 v 10.6 v uvlo soft start i vcc 130 a 1.6 v v res i res -21.3 a i lvs > 18 a < 160 a < 6.0 ma + i gate < 210a pp v bus 95 % 30 % 17.5 v 100 % 1 2 3 4 135 khz 100 khz frequency lamp voltage frequency / lamp voltage monitoring start up figure 5 progress of level during a typical start ? up 1 i gate depends on mosfet
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 14 of 55 ICB2FL02G v1.2 functional description in case of v cc exceeds the 10.6 v level and stays below 14. 1 v (start up hysteresis ? phase 2 figure 5), the ic checks whether the lamps are assembl ed by detecting a current across the filaments. the low side filaments are checked fr om a source current of typical i res3 = - 21.3 a out of pin 12 res (figure 5 i res ). this current produces a voltage drop of v res < 1.6 v (filament is ok) at the low side filament sense resistor (r 36 in figure 3), connec ted to gnd (via low side filament). an open low side filament is detected (see chapter 2.3.2), when the voltage at the res pin exceeds the v res > 1.6v threshold (figure 5 v res ). the high side filaments are checked by a current of i lvs > 12 a typically via re sistors r41, r42, r43 and r44 (figure 3) into the lvs1 pin 13 (for a single lamp operation) and lvs2 pin 14 for a multi lamp operation. note: in case of a single lamp operation, the unused lvs pin has to be disabled via connection to gnd. an open high side filament is detected (see 2.3.3) when there is no sink current into the lvs pin. this causes a higher source cu rrent out of the res pin (t ypical 42.6 a / 35.4 a) in order to exceed v res > 1.6 v. in case of defect filaments, the ic keeps monitoring until there is an adequate current from the res or the lvs pin pres ent (e.g. in case of removal a defect lamp). when v cc exceeds the 14.1 v threshold - by the end of t he start up hysteresis in phase 2 figure 5 - the ic waits for 130s and senses the bus voltage. when the rated bus voltage is in the corridor of 12.5% < v busrated < 105% the ic powers up the system and enters phase 3 (figure 5 v busrated > 95 % sensing) when not, the ic initiates an uvlo when the chip supply voltage is below v cc < 10.6 v. as soon as the condition for a power up is fulfilled, the ic starts the inverter gate operation with an internal fixed start up frequency of 135 khz. the pfc gate drive starts with a delay of app. 300s. now, the bus voltage will be checked for a rated level above 95 % for a duration of 80 ms (phase 3 figure 5). when leaving phase 3, the ic enters t he soft start phase and shifts the frequency from the internal fixed start up frequency of 135 khz down to the set preheating frequency e.g. f rfph = 100 khz.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 15 of 55 ICB2FL02G v1.2 functional description 2.2.2 operating levels from soft start to run mode this chapter describes the operating flow from ph ase 5 (preheating mode) until phase 8 (run mode) in detail. in order to extend the life time of the f ilaments, the controller enters - after the soft start phase - the preheating mode (phase 5 figure 6). th e preheating frequency is set by resistors r22 pin rfph to gnd in combination with r21 (figure 3) typ. 100 khz e.g. r22 = 8.2 k ? in parallel to r21 = 11.0 k ? see figure 3 at the r frun - pin). the preheating time can be selected by the programming resistor (r23 in figure 3) at pin rt ph from 0 ms up to 2500 ms (phase 5 figure 6). figure 6 typical variation of operating frequency during start up during ignition (phase 6 figure 6), the operating fr equency of the inverter is shifted downward in t typ = 40 ms (t max = 237 ms) to the run frequency set by a resistor (r21 in figure 3) at pin rfrun to gnd (typical 45 khz with 11.0 k ? resistor). during this frequency sh ifting, the voltage and current in the resonant circuit will rise when the operation is close to the resonant frequency with increasing voltage across the lamp. the ignition control is activated if the sensed slope at the lscs pin reaches typically 205 mv/s 25 mv/s and exceeds the 0.8v threshol d. this stops the decreasing of the frequency and waits for ignition. the ignition control is now continuously monitored by the lscs pin. the maximum duration of the ignition procedure is limited to 237 ms. is there no ignition within this time frame, the ignition control is disabled and the ic changes over into the latched fault mode. furthermore, in order to reduce the lamp choke, t he ignition control is designed to operate with a lamp choke in magnetic saturation during ignition. for an operation in magnetic saturation during ignition; the voltage at the shunt at the lscs pin 1 has to be v lscs = 0.75v when ingition voltage is reached. if the ignition is successful, the ic enters the pre ? run mode (phase 7 figure 6). the pre run mode is a safety mode in order to prevent a malfunction of the ic due to an instable system e.g. the lamp parameters are not in a steady st ate condition. after 625 ms pre ru n mode, the ic changes into the run mode (phase 8 figure 6). the run mode monitors the complete system regarding bus over- and under voltage, open loop, over current of pfc and / or in verter, lamp over voltage (eol1) and rectifier effect (eol2) (see chapter 2.5) and capacitive load 2 (see chapter 2.6).
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 16 of 55 ICB2FL02G v1.2 functional description figure 7 shows the lamp voltage versus the frequency during the different phases from preheating to the run mode. the lamp voltage rises by the end of the preheating phase with a decreasing frequency (e.g. 100 khz to 50 khz) up to 700 v during i gnition. after ignition, the lamp voltage drops down to its working level with continuo decreasing the frequency (figure 7) down to its working level e.g. 45 khz (set by a resistor at the r frun pin to ground). after stops the decreasing of the frequency, the ic enters the pre run mode. lamp voltage vs frequency @ different modes 0 100 200 300 400 500 600 700 800 900 1000 10000 100000 frequency [hz] lamp voltage [v] 0 100 200 300 400 500 600 700 800 900 1000 after ignition before ignition figure 7 lamp voltage versus frequency during the different start up phases
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 17 of 55 ICB2FL02G v1.2 functional description 2.3 filament detection during start up and run mode the low and high side filament detection is sens ed via the res and the lvs pins. the low side filament detection during start up and run mode is detected via the res pin only. an open high side filament during start up will be sensed via the lvs and the res pins. 2.3.1 start up with broken low side filament a source current of i res3 = - 21.3 a out of the res pin (12) monitors during a start up (also in run mode) the existence of a low side filament. in ca se of an open low side filament during the start up hysteresis (10.6v < v cc < 14.1v) a capacitor (c19 in figure 3) will be charged up via i res3 = - 21.3 a. when the voltage at the res pin (12) exceeds v res1 = 1.6 v, the controlle r prevents a power up and clamps the res voltage internally at v res = 5.0 v. the gate drives of the pfc and inverter stage do not start working. 21.3a 10.6 v no power up 14.1 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v start up with open low side filament time v res 1.3 v 1.6 v 5.0 v v cc time v lamp time time 17.7a i res figure 8 startup with open low side filament figure 9 restart from open low side filament the ic comparators are set now to a threshold of v res1 = 1.3v and to i res4 = - 17.7a, the controller waits until the voltage at the res pin drops below v res1 = 1.3v.when a filament is present (figure 9 section 2), the voltage drops below 1.3v and the value of the source current out of the res pin is set from i res4 = - 17.7 a up to i res3 = - 21.3 a. now the controller powers up the system including soft start and preheating into the run mode.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 18 of 55 ICB2FL02G v1.2 functional description 2.3.2 low side filament detection during run mode in case of an open low side filament during run mode, the current out of the res pin i res3 = - 21.3 a charges up the capacitor c19 in figure 3. if the voltage at the res pin exceeds the v res3 = 3.2v threshold, the controller detects an open low side f ilament and stops the gate drives after a delay of t = 620s of an internal timer. v cc / v pfcgd time 10.0 v 16.0 v chip supply voltage 17.5 v open low side filament during run mode time v res 1.3 v 3.2 v 5.0 v time time v lamp 21.3a i res pfc gate drive delay t = 620s 17.7a 1.6 v latch mode figure 10 open low side filament run mode i res 10.0 v latch mode 16.0 v chip supply voltage 17.5 v restart from open low side filament time v res 1.3 v 1.6 v 5.0 v time time v lamp time power up into run mode pfc gate drive 1 2 3 timer t = 100ms 21.3a 17.7a figure 11 restart from open ls filament a restart is initiated when a filament is detected e.g. in case of a lamp removal. in case of a filament is present (figure 11 section 2), the voltage drops below 1.3v and the value of the source current out of the res pin is set from i res4 = - 17.7 a up to i res3 = - 21.3 a. the controller powers up the system including soft start and preheating into the run mode (figure 11 section 3).
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 19 of 55 ICB2FL02G v1.2 functional description 2.3.3 start up with broken high side filament an open high side filament during the start up hysteresis (10.6v < v cc < 14.1v) is detected, when the current into the lvs pin 13 or 14 is below i lvs = 12 a (typically). in that case, the current out of the res pin 12 rises up to i res1 = - 42.6 a. that causes a voltage at the res pin crosses v res1 = 1.6v. the source current is now set to i res2 = - 35.4 a and another threshold of v res2 = 1.3v is active. the controller prevents a power up (see figure 12), the gate drives of the pfc and inverter stage do not start working. i res 10.6 v no power up 14.1 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v start up with open high side filament time v res 1.3 v 1.6 v v cc time time 42.6a 35.4a 21.3a v lamp i res time 17.7a 2.0 v time i lvs 12a i lvs figure 12 start up with open high side filament 10.6 v no power up 14.1 v 16.0 v chip supply voltage 17.5 v restart from open high side filament time v res 1.3 v 1.6 v 2.0 v v cc time time i res v lamp i res time power up (into run mode) time i lvs i lvs 12a 42.6a 35.4a 21.3a 17.7a figure 13 restart from open high side filament when the high side filament is present, e.g. insert a lamp, the current of the active lvs pins exceeds i lvs > 12 a (typically), the res current drops from i res2 = - 35.4 a down to i res4 = - 17.7 a (figure 13). now the controller senses the low side filament. when a low side filament is also present, and the controller drops (after a short delay due to a capacitor at the res pin) below v res2 = 1.3v, the res current is set to i res3 = - 21.3 a, the controller powers up the system.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 20 of 55 ICB2FL02G v1.2 functional description 2.4 pfc pre converter 2.4.1 discontinuous conduction and critical conduction mode operation the digital controlled pfc pre converter starts wi th an internally fixed on time of typical t on = 4.0s and variable frequency. the on ? time is enlarged every 280 s (typical) up to a maximum on ? time of 22.7 s. the control switches quite immediat ely from the discontinuous conduction mode (dcm) over into critical conduction mode (critcm) as soon as a sufficient zcd signal is available. the frequency range in critcm is 22 khz until 500 khz, depending on the power (figure 14) with a variation of the on time from 22.7 s > t on > 0.5s. discontinuous conduction mode (dcm) <> critical condution mode (critcm) 0,01 0,10 1,00 10,00 100,00 1000,00 0,01 0,10 1,00 10,00 100,00 normalized output power [% ] pfc frequency [khz] 50% duty cycle 0,10 1,00 10,00 100,00 pfc - on time [s] frequency dcm frequency critcm ton dcm ton critcm figure 14 operating frequency and on time versus power in dcm and critcm operation for lower loads (p outnorm < 8 % from the normalized load 2 ) the control operates in discontinuous conduction mode (dcm) with an on ? time from 4.0s and increasing off ? time. the frequency during dcm is variable in a range from 144 khz down to typically 22 khz @ 0.1 % load (figure 14). with this control method, the pfc converter enables a stable operation from 100 % load down to 0.1 %. figure 14 shows the on time range in dcm and cr itcm (critical conduction mode) operation. in the overlapping area of critcm and dcm is a hyster esis of the on time which causes a negligible frequency change. 2 normalized power @ low line input voltage and maximum load
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 21 of 55 ICB2FL02G v1.2 functional description 2.4.2 pfc bus voltage sensing over voltage, open loop, bus 95 % and under voltage st ates (figure 15) of the pfc bus voltage are sensed at the pfcvs pin via the network r14, r 15, r20 and c11 figure 3 (c11 acts as a spike suppression filter). 2.4.2.1 bus over voltage and pfc open loop the bus voltage loop control is completely integrat ed (figure 16) and provided by an 8 bit sigma ? delta a/d ? converter with a typical sampling rate of 280 s and a resolution of 4 mv/bit. after leaving phase 2 (monitoring), the ic starts the power up (v cc > 14.1v). after power up, the ic senses for 130s the bus voltage below 12.5% (open loop) or a bove 105% (bus over voltage). in case of a bus over voltage (v busrated > 109 %) or open loop (v busrated < 12.5 %) in phases 3 until 8 the ic shuts off the gate drives of the pfc within 5s respective in 1s. in this case, the pfc restarts automatically when the bus voltage is within the corridor (12.5% < v busrated < 105 %) again. is the bus voltage after the 130s valid, the bus voltage sensing is set to 12.5% < v busrated < 109 %. in case leaving these thresholds for longer than 1s (open loop) or 5s (overvoltage) the pfc gate drive stops working until the voltage drops below 105% or ex ceeds the 12.5% level. if the bus over voltage (>109%) lasts for longer than 625ms in run mode, the inverter gates also shut off and a power down with complete restart is attempt (figure 15). figure 15 pfc bus voltage operating level and error detection 2.4.2.2 bus voltage 95% and 75% sensing when the rated bus voltage is in the corridor of 12.5% < v busrated < 109 %, the ic will check whether the bus voltage exceeds the 95 % threshold (figure 15 phase 3) within 80 ms before entering the soft start phase 4. another threshold is activated wh en the ic enters the run mode (phase 8). when the rated bus voltage drops below 75% for longer than 84 s, a power down with a complete restart is attempted when a counter exceeds 800 ms. in case of a short term bus under voltage (the bus voltage reaches its working level in run mode before exce eding typically 800 ms (min. 500ms) the ic skips phases 1 until 5 and starts with igniti on (condition for emergency lighting see 2.7.1). the internal reference level of the bus voltage sense v pfcvs is 2.5 v (100 % of the rated bus voltage) with a high accuracy. a surge protection is activated in case of a rated bus voltage of v bus > 109% and a low side current sense voltage of v lscs > 0.8v for longer as 500ns in pre run and run mode.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 22 of 55 ICB2FL02G v1.2 functional description 2.4.3 pfc structure of mixed signal a digital notch filter eliminates the input voltage ripple - independent from the mains frequency. a subsequent error amplifier with pi characteristic cares for a stable operation of the pfc pre converter (figure 16). figure 16 structure of the mixed digital and analog control of the pfc pre converter the zero current detection (zcd) is sensed by the pfczcd pin via r13 (figure 3). the information of finished current flow during demagnetization is requir ed in critcm and in dcm as well. the input is equipped with a special filtering including a blanki ng of typically 500 ns and a large hysteresis of typically 0.5 v and 1.5 v v pfczcd (figure 16).
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 23 of 55 ICB2FL02G v1.2 functional description 2.4.4 thd correction via zcd signal an additional feature is the thd correction (figur e 16). in order to optimize the improved thd (especially in the zones a shown in figure 17 zc d @ ac input voltage), there is a possibility to extend pulse width of the gate signal (blue part of the pfc gate signal in figure 17) via variable pfc zcd resistor (see resistor r13 in figure 3) in addition to the gate signal controlled by the v pfcvs signal (gray part of the pfc gate signal in figure 17). figure 17 thd optimization using adjustable pulse width extension in case of dc input voltage (see dc input voltage in figure 17), the pulse width gate signal is fixed as a combination of the gate signal controlled by the v pfcvs pin (gray) and the additional pulse width signal controlled by the zcd pin (blue) shown in figure 17 zcd @ dc input voltage. the pfc current limitation at pin pfccs interrupts the on ? time of the pfc mosfet if the voltage drop at the shunt resistors r18 (figure 3) exceeds the v pfccs = 1.0 v (figure 16). this interrupt will restart after the next sufficient signal from zcd is available (auto restart). the first value of the resistor can be calculated by the ratio of the pfc mains choke and zcd winding the bus voltage and a current of typically 1.5 ma (see equation below). an adjustment of the zcd resistor causes an optimized thd. ma v n n r bus pfc zcd zcd 5 . 1 * = equation 1 r zcd a good pratical value
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 24 of 55 ICB2FL02G v1.2 functional description 2.4.5 optional thd correction dedicated for dcm operation for applications with a wide input voltage range and / or for applications using a wide variation of the power e.g. dimming, the application might work in the dcm (discontinuous conduction mode). in order to minimize the high order harmonics during dcm, the detection of the dcm should be as close as possible at the point of inflection of the pfc drain source voltage shown in figure 18. figure 18 signal shapes with optional damping of oscillations during dcm operation of pfc. this can be realized with an optional damping network (r4, d10 and q4 see figure 19) from the aux pin to the zcd resistor r13. figure 19 optional circuit for attenuating oscillations during dcm operation of pfc
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 25 of 55 ICB2FL02G v1.2 functional description 2.5 detection of end-of-life and rectifier effect two effects are present by end of life (eol): lamp over voltage (eol1) and a rectifier effect (eol2). after ignition (see 1 in figure 20), the lamp voltage breaks down to its run voltage level with decreasing frequency. by reaching the run frequency, the ic enters the pre run mode for 625 ms. during this period, the eol detection is still disabl ed. in the subsequent run mode (2 in figure 20) the detection of eol1 (lamp over voltage see 3 figure 20) and eol2 (rectifier effect see 4 figure 20) is complete enabled. figure 20 end of life and rectifier effect 2.5.1 detection of end of life 1 (eol1) ? lamp overvoltage the event of eol1 is detected by measuring the po sitive and negative peak level of the lamp voltage via an ac current fed into the lvs pin (figure 21). th is ac current is fed into the lvs pins (lvs1 for single lamp and lvs2 for multi lamp applications ) via network r41, r42, r43, r44 and the low pass filter c40 and r45 see figure 3. if the sensed ac current exceeds 210 a pp for longer than 620 s, the status of end-of-life (eol1) is detected (lamp overvoltage / overload see figure 21 lvsac current). the eol1 fault results in a latched power down mode (after trying a single restart) the controller is continuously monitoring the status unt il eol1 status changes e.g. a new lamp is inserted. figure 21 end of life (eol1) detection, lamp voltage versus ac lvs current
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 26 of 55 ICB2FL02G v1.2 functional description 2.5.2 detection of end of life 2 (eol2) ? rectifier effect the rectifier effect (eol2) is detected by measur ing the positive and negative dc level of the lamp voltage via a current fed into the lvs pin (figure 22). this current is fed into the lvs pins (lvs1 for single lamp and lvs2 for multi lamp applications) via network r41, r42, r43 and r44 (see figure 3). if the sensed dc current exceeds 42 a (figure 22 lvsdc current) for longer than 2500 ms, the status of end-of-life (eol2) is detected. the eo l2 fault results in a latched power down mode (after trying a single restart) the controller is continuous ly monitoring. the insert of a new lamp or the interruption of the input voltage resets the status of the ic. figure 22 end of life (eol2) detection, lamp voltage versus dc lvs current
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 27 of 55 ICB2FL02G v1.2 functional description 2.6 detection of capacitive load in order to prevent a malfunction in the area of capacitive load (see figure 23) during run mode due to certain deviations from the normal load (e.g. harmed lamp, sudden break of the lamp tube ?), the ic has two integrated thresholds ? sensed only via the lscs (pin 1). the controller detects working with short over current (capload 2). this state (capload 2) is affecting an operation below the resonance in the capacitive load area (figure 23). in this case the ic results in a latched power down mode after a single restart. after latching the power down mode, the controller is continuously monitoring the input voltage and lamp filaments and restarts after interrupting the input voltage or inserting a new lamp. lamp voltage vs frequency @ different modes 0 100 200 300 400 500 600 700 800 900 1000 10000 100000 frequency [hz] lamp voltage [v] 0 100 200 300 400 500 600 700 800 900 1000 after ignition before ignition ignition after ignition pre run and run mode pre heating area of capacitive load behavior load area of inductive load behavior figure 23 capacitive and inductive operation
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 28 of 55 ICB2FL02G v1.2 functional description 2.6.1 capacitive load 2 (over cu rrent / operation below resonance) a capacitive load 2 operation is detected if t he voltage at the lscs pin drops below a second threshold of v lscs = ? 50 mv directly before the high side mosfet is turned on or exceeds a third threshold of v lscs = 2.0 v during on switching of the high si de mosfet. if this over current is present for longer than 620 s, the ic results a latched power down mode after trying a single restart. the controller keeps monitoring continuously the status until an adequate load is present e.g. a new lamp is inserted, then the ic changes into a normal operation. figure 24 capacitive mode 2 ? operation with over current
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 29 of 55 ICB2FL02G v1.2 functional description 2.6.2 adjustable self adapting dead time the dead time between the turn off and turn on of the half ? bridge drivers is adjustable (c16 see figure 3) and detected via a second threshold (? 50 mv) of the lscs voltage. the range of the dead time adjustment is 1.05 s up to 2.0 s durin g all operating modes. start of the dead time measurement is the off switching of the hi gh side mosfet. the finish of the dead time measurement is, when v lscs drops for longer than typical 280ns (internal fixed propagation delay) below -50mv. this time will be stored (stored d ead time) and the low side gate driver switches on. the high side gate driver turns on again after o ff switching of the low side switch and the stored dead time. figure 25 dead time of on and off of the half bridge drivers
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 30 of 55 ICB2FL02G v1.2 functional description 2.7 emergency lighting line interruptions (bus voltage drops) are detected by the pfcvs. if the rated pfc bus voltage drops below v busrated < 75 % during run mode, the controller detec ts a pfc bus under voltage. in order to meets the emergency lighting standards, the controller distinguishes two different states of a pfc bus under voltage, a short and a long term pfc bus under voltage. a timer increases the time as long as a bus under voltage is present. a short term bus under voltage is detected if the timer value stays below t < 800ms typically (500ms min.) after the bus volt age reaches the nominal level again. these causes a restart without preheating (emergency standard of vde0108) see figure 26. when the timer exceeds t > 800 ms, the controller forces a comple te restart of the system due to a long term bus under voltage (figure 27).
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 31 of 55 ICB2FL02G v1.2 functional description 2.7.1 short term pfc bus under voltage a short term pfc bus under voltage (figure 26) is detected if the duration of the under voltage does not exceed 800 ms (timer stays below t < 800ms s ee figure 26). in that case, the pfc and inverter drivers are immediately switched off and the controller is continuously monitoring the status of the bus voltage in a latched power down mode (i cc < 170 a). if the signal at the lvs pin exceeds 18a and the rated bus voltage is above 12.5% within the timer is below t < 800 ms, the controller restarts from power up without preheating. the timer re sets to 0 when entering the run mode. bus voltage drop for t < 800 ms restart without preheating 100% 75% v busrated v cc 16v i preheating v lamp i cc < 6 ma + i qgate < 160 a < 6 ma + i qgate interrupt for t < 800 ms timer t = 800ms run mode power down mode pre run run mode figure 26 bus voltage drop below 75% (rated bus voltage) for t < 800 ms during run mode
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 32 of 55 ICB2FL02G v1.2 functional description 2.7.2 long term pfc bus under voltage if the duration of the bus under voltage exceeds t > 800ms see figure 27, the controller forces an under voltage lock out (uvlo). the chip supply voltage drops below v cc = 10.6 v and the chip supply current is below i cc < 130a. when the vcc voltage exceeds the 10.6v threshold again, the ic current consumption is below i cc < 160a. in that case, the controller rese ts the timer and restarts with the full start up procedure including monitoring, power up, start up, soft start, preheating, ignition, pre run and run mode as shown in figure 27. 95% 75% v busrated v cc 16v i preheating v lamp i cc < 6 ma + i gate < 160 a < 6 ma + i gate interrupt for t > 800 ms timer t = 800ms uvlo @ 10.6v bus voltage drop for t > 800 ms restart with full start procedure run mode power down mode run mode <160 a figure 27 bus voltage drop below 75% (rated bus voltage) for t > 800 ms during run mode
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 33 of 55 ICB2FL02G v1.2 functional description 2.8 built in customer test mode operation in order to decrease the final ballast testing time for customers, the 2 nd generation of ballast ic supports an integrated built in customer test mode and several functions to disable some features and states of the ic. 2.8.1 pre heating test mode this feature forces the ic to stay in the pre heating mode (see chapter 2.8.1.2) or to starts the ignition immediately without any preheating (see chapter 2.8.1.1 skip pre heating). a resistor at this pin defines the duration of the pre heating phase. norm ally, the pre heating phase is in a range of 0ms up to 2500ms set via a resistor r rtph = 0 ? up to 25k ? from the rtph pin to gnd. the pre heating phase is skipped when the rthp pin is set to gnd. if the signal at this pin is v rtph > 5.0 v, the ic remains in the pre heating mode. 2.8.1.1 skip the pre heating phase ? set rtph pin to gnd the pre heating phase can be skipped in set the rtph pin 11 to gnd. figure 28 shows a standard start up with a set pre heating time via resistor at the rtph pin 11 to gnd (e.g. 8.2 k ? this is equal to a pre heating phase of app. 820ms). the pre heating phase can be skipped in setting the rtph pin 11 directly to gnd. in that case, the igniti on is directly after the soft start phase. figure 28 start up with pre heating figure 29 start up without pre heating
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 34 of 55 ICB2FL02G v1.2 functional description 2.8.1.2 ic remains in pre heating phase this feature gives the customer the flexibility to a lign the pre heating frequency to the filament power in the pre heating phase. figure 30 shows a standar d start up with the set preheating time of e.g. 820ms with an 8.2 k ? resistor at the rtph pin 11. to force the ic remains in pre heating, the voltage level at the rtph pin 11 has to set to 5.0 v. the dur ation of this 5.0 v signal defines the time of the pre heating see i preheat in figure below. 10.6 v 14.1 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v time v rtph 2.5 v v cc time v lamp time i preheat time preheating t = 820 ms when using rrtph = 8.2kohm ignition duration is set by resistor only 5.0 v figure 30 start up with pre heating figure 31 start up ic remains in pre heating
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 35 of 55 ICB2FL02G v1.2 functional description 2.8.2 deactivation of the filament detection in order to deactivate the filament detection of the low or high side filament, set the res pin 12 or the lvs1 / lvs2 pin 13 / 14 to gnd. in that case, the ic starts up into normal operation without checking the filaments e.g. when using an equivalent lamp resistive load instead of a load. 10.6 v 14.1 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v time v res 1.3 v 1.6 v 5.0 v v cc time time 10v v lamp time res pin set to gnd figure 32 deactivation via res pin 10.6 v 14.1 v 16.0 v start up hysteresis uvlo chip supply voltage 17.5 v v res 1.3 v 1.6 v 5.0 v v cc time v lsgd v lamp lvs1 or lvs2 pin set to gnd 10v figure 33 deactivation via lvs1 / lvs2 pin figure 32 shows the deactivation of the low and hi gh side filament via set the res pin 12 to gnd. figure 33 shows the deactivation of the high side filam ent detection via set the lvs1 or lvs2 pin to gnd. note in case using just one path of a ballast design (singl e or dual lamp in series) one of the not used lvs pins has to be set to gnd.
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 36 of 55 ICB2FL02G v1.2 functional description 2.8.3 built in customer test mode (clock acceleration) the built in customer test mode, supported by this ic, saves testing time for customers in terms of ballast end test. in that mode, the ic accelerates the internal clock in order to reduce the time of the 4 different procedures by the following factors (see table 1). phase duration for test [ms] acceleration factor nominal duration [ms] preheating 625 4 2500 (max) time out ignition 118.5 2 237 pre run mode 41.7 15 625 eol2 41,7 60 2500 table 1 specified acceleration factors 2.8.3.1 enabling of th e clock acceleration the clock acceleration (built in customer test mode) is activated when the chip supply voltage exceeds v cc > 14.1v and the voltages at the run frequen cy and preheating frequency pin are set to v rfrun = v rfph = 5.0 v ( 5 %) see figure 34 clock acceleration (built in customer test mode). a res pin voltage of v res > 3.5 v up to 5.0 v ( 5 %) prevents a power up of the ic, the ic remains in a mode before powering up. this status is hold as long as the voltage at the res pin is at v res > 3.5 v up to 5.0 v ( 5 %) ? no power up. note: after the activation of the clock acceleration mode, the voltage level of 5.0v at the run fr equency and preheating frequency pin (v rfrun = v rfph ) can be released. 2.8.3.2 starting the chip with accelerated clock in order to start the ic with an accelerated clock, set the voltage at the res pin to gnd (v res = 0 v). figure 34 clock acceleration (built in customer test mode). the ic powers up the system and starts working with an accelerated clock. now the duration of the different modes ar e accelerated by factors shown in table 1. figure 34 clock acceleration (built in customer test mode)
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 37 of 55 ICB2FL02G v1.2 state diagram 3 state diagram 3.1 features during different operating modes 0...80ms start-up 10ms softstart 10.6v < vcc < 17.5v f= f_ph 0...2500ms preheating 40...237ms ignition 625ms pre-run run 10.6v < vcc < 17.5v f= f_run mains switch turned on; 0v < vcc < 10.6v; i_vcc < 130a; i_res= 0a typ. 35ms monitoring typ. 60ms uvlo bus overvoltage > 109% bus undervoltage < 75% bus open loop < 12,5% overcurrent pfc overcurrent inverter capacitive load 2 eol 1, overload eol 2, rectifier effect enabled pfc enabled pfc enabled enabled 1,6v enabled enabled 1,6v enabled enabled 0,8v enabled enabled enabled pfc 5s enabled inv 625ms enabled 84s enabled 200ns threshold 1.0v enabled 620s u u u n f f a = auto restart n = no fault u = undervoltage f = fault, a single restart minimum duration of effect vcc > 14.1v & filament detected; 12,5%< vbus <105% => start after 130s f_start = 135khz as long as vbus < 95% f f 10.6v < vcc < 17.5v vbus > 95% f_start > f > f_ph 10.6v < vcc < 17.5v f_ph > f > f_run enabled pfc 10.6v < vcc < 17.5v; i_res= 21.3a; f= f_run 10.6v < vcc < 14.1v; i_vcc < 160a; i_res= 21.3a fault: 10.6v < vcc < 17.5v; i_vcc < 170a; i_res= 21.3a disabled by lamp removal or uvlo f= a single restart is possible afte r delay of 200ms by internal timer enabled 2,5s bus undervoltage < 95% a enabled pfc enabled pfc enabled pfc enabled pfc enabled pfc enabled pfc enabled enabled 1,6v enabled 1,6v enabled 500ns threshold 0.8v enabled 620s bus overvoltage > 105% a enabled 130s enabled pfc 5s enabled inv 625ms enabled pfc figure 35 monitoring features during different operating modes
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 38 of 55 ICB2FL02G v1.2 state diagram 3.2 operating flow of the start up procedure into the run mode after 130s & v bus > 12,5% & v bus < 105% vcc > vccon(14.1v) & filament detected v bus > 95% within 80ms vcc > 10.6v v bus < 12,5% or v bus > 105% after 10ms & flag skip preheat = reset after t_ph= 0...2500ms time set by r_tph f_inv= f_run within t_ign= 40...237ms after t_prerun= 625ms uvlo vcc < 10.6v icc < 130a monitoring vcc > 10.6v icc < 160a power-up gate drives off 14.1v < vcc icc approx 6.0ma start-up inverter gates on pfc gate on 17.5v> vcc >10.6v f_inv = f_start softstart 17.5v> vcc >10.6v f_start=> f_ph preheat 17.5v> vcc >10.6v f = f_ph ignition* timeout 237ms 17.5v> vcc >10.6v f_ph => f_run pre-run 17,5v> vcc >10.6v f = f_run reduced monitoring run 17.5v> vcc >10.6v f = f_run complete monitoring after 10ms & flag skip preheat = set // reset flag skip preheat & counter skip ph // fault 17.5v> vcc >10.6v icc < 170a gate drives off see protection functions see timing and handling of fault conditions * note: ignition will reset the flag skip preheating vcc < 10.6v figure 36 operating flow during start-up procedure
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 39 of 55 ICB2FL02G v1.2 state diagram 3.3 auto restart and latched fault condition mode figure 37 operating process during start-up mode and handling of fault conditions
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 40 of 55 ICB2FL02G v1.2 4 protection functions matrix description of fault characteristics of fault o perating mode detection is active consequence name of fault type of fault minimum duration of effect monitoring power-up 130s start-up until vbus > 95% softstart 10ms preheat mode 0 ? 2500ms ignition mode 40 ? 237ms pre-run mode 625ms run mode supply voltage vcc < 14.1v before power up below start- up threshold s 1s x prevents power up supply voltage vcc < 10.6v after power up below uvlo threshold s 5s x x x x x x x x power down, reset failure latch current into lvs1 pin <18a before power up open filament hs s 100s x prevents power up current into lvs2 pin <18a before power up open filament hs s 100s x prevents power up voltage at res pin > 1.6v before power up open filament ls s 100s x prevents power up voltage at res pin > 3.2v open filament ls f 620s x power down,latched fault mode, 1 restart bus voltage < 12.5% of rated level 10s after power up open loop detection s 1s x keep gate drives off, re- start after vcc hysteresis bus voltage < 12.5% of rated level open loop detection n 1s x x x x x x stops pfc fet until vbus > 12.5% bus voltage < 12.5% of rated level shut down option u 625ms x power down, restart when vbus> 12.5% bus voltage < 75% of rated level add. shut down delay 120s under- voltage u 84s x power down, 100ms delay, restart, skip pre- heating max 7 times bus voltage < 95% of rated level during start-up timeout max start-up time a 80ms x power down, 200ms delay, restart bus voltage > 105% of rated level 10s after power up over- voltage s 5s x keep gate drives off, re- start after vcc hysteresis bus voltage > 109% of rated level in active operation pfc overvoltage n 5s x x x x x x stops pfc fet until vbus< 105% bus voltage > 109% of rated level in active operation inverter overvoltage u 625ms x power down, restart when vbus<105% +/- peak level of lamp voltage at pin lvs above threshold eol 1 overvoltage f 620s x power down,latched fault mode, 1 restart dc level of lamp voltage above +/- threshold eol 2 rect. effect f 2500ms x power down,latched fault mode, 1 restart capacitive load 2, operation below resonance cap.load 2 overload f 620s x power down,latched fault mode, 1 restart run frequency cannot be achieved timeout ignition f 237ms x power down,latched fault mode, 1 restart voltage at pfccs pin > 1.0v pfc overcurrent n 200ns x x x x x x stops on-time of pfc fet immediately voltage at lscs pin > 0.8v inverter current lim n 200ns x activates ignition control voltage at lscs pin > 0.8v inverter overcurrent f 500ns x x power down,latched fault mode, 1 restart voltage at lscs pin > 1.6v inverter overcurrent f 500ns x x x x power down,latched fault mode, 1 restart voltage at lscs pin > 0.8v & vbus > 109% (surge) inverter overcurrent a 500ns x x power down, restart when vbus<109% after jump into latched fault mode f wait 200ms a si ngle restart attempt after delay of internal timer reset of failure latch in run mode after 40s rese t of failure latch by uvlo or 40s in run mode s = start-up condition, n = no fault, a = auto-restart , u = undervoltage f = fault with a single restart, a second f leads to a latched fault / note: all values @ typica l 50 hz mains frequency
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 41 of 55 ICB2FL02G v1.2 electrical characteristics 5 electrical characteristics note: all voltages without the high side signals are measured with respect to ground (pin 4). the high side voltages are measured with respect to pin17. the voltage levels are valid if other ratings are not violated. absolute maximum ratings 5.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capacitor that will be connected to pin 3 (v cc ) and pin 18 (hsvcc) is discharged before assembling the application circuit. parameter symbol limit values unit remarks min. max. lscs voltage v lscs - 5 6 v lscs current i lscs - 3 3 ma lsgd voltage v lsgd - 0.3 v cc +0.3 v internally clamped to 11v lsgd peak source current i lsgdsomax - 75 5 ma < 500ns lsgd peak sink current i lsgdsimax - 50 400 ma < 100ns vcc voltage v vcc - 0.3 18 v vcc zener clamp current i vcczener - 5 5 ma ic in power down mode pfcgd voltage v pfcgd - 0.3 v cc +0.3 v pfcgd peak source current i pfcgdsomax - 150 5 ma < 500ns pfcgd peak sink current i pfcgdsimax - 100 700 ma < 100ns pfccs voltage v pfccs - 5 6 v pfccs current i pfccs - 3 3 ma pfczcd voltage v pfczcd - 3 6 v pfczcd current i pfczcd - 5 5 ma pfcvs voltage v pfcvs - 0.3 5.3 v rfrun voltage v rfrun - 0.3 5.3 v rfph voltage v rfph - 0.3 5.3 v rtph voltage v rtph - 0.3 5.3 v res voltage v res - 0.3 5.3 v lvs1 voltage v lvs1 - 6 7 v lvs1 current1 i lvs1_1 - 1 1 ma ic in power down mode lvs1 current2 i lvs1_2 - 3 3 ma ic in active mode lvs2 voltage v lvs2 - 6 7 v lvs2 current1 i lvs2_1 - 1 1 ma ic in power down mode lvs2 current2 i lvs2_2 - 3 3 ma ic in active mode
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 42 of 55 ICB2FL02G v1.2 absolute maximum ratings parameter symbol limit values unit remarks min. max. aux voltage v aux - 0.3 5.3 v hsgnd voltage v hsgnd - 900 900 v referring to gnd hsgnd voltage transient d v hsgnd /dt - 40 40 v/ns hsvcc voltage v hsvcc - 0.3 18 v referring to hsgnd hsgd voltage v hsgd - 0.3 v hsvcc +0.3 v internally clamped to 11v hsgd peak source current i hsgdsomax - 75 0 ma < 500ns hsgd peak sink current i hsgdsimax 0 400 ma < 100ns junction temperature t j - 25 150 c storage temperature t s - 55 150 c maximum power dissipation p tot ? 2 w pg_dso-19-1 t amb =25c thermal resistance (2 chips) r thja ? 60 k/w pg_dso-19-1 thermal resistance (hs chip) r thjahs ? 120 k/w pg_dso-19-1 thermal resistance (ls chip) r thjals ? 120 k/w pg_dso-19-1 soldering temperature ? 260 c wave soldoldering 1) esd capability v esd ? 2 kv human body model 2) creepage distance hs vs. ls 1.9 2.0 mm rated bus voltage (95%) v pfcvs95 2.33 2.43 v 1) according to jesd22a111 2) according to eia/jesd22-a114-b (discharging an 100 pf capacitor through an 1.5k ? series resistor)
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 43 of 55 ICB2FL02G v1.2 operating range 5.2 operating range parameter symbol limit values unit remarks min. max. hsvcc supply voltage v hsvcc v hsvccoff 17.5 v referring to hsgnd hsgnd voltage v hsgnd - 900 900 v referring to gnd vcc voltage @ 25c v vcc v vccoff 17.5 v t j = 25c vcc voltage @ 125c v vcc v vccoff 18.0 v t j = 125c lscs voltage range v lscs - 4 5 v in active mode pfcvs voltage range v pfcvs 0 4 v pfccs voltage range v pfccs - 4 5 v in active mode pfzcd current range i pfczcd - 3 3 ma in active mode lvs1, lvs2 voltage range v lvs1,lvs2 - 6 6 1) v lvs1, lvs2 current range i lvs1,lvs2 2) 210 a ic power down mode lvs1, lvs2 current range i lvs1,lvs2 - 2.5 2.5 ma ic active mode rfph frequency f rfphrange f run 150 khz rfph source current range i rfph - 500 0 a @ v rfph = 2.5v rtph voltage range v rtph 0 2.5 v junction temperature t j - 25 125 c adjustable preheating freq. f rfph f rfrun 150 khz range set by rfph adjustable run frequency f rfrun 20 120 3) khz range set by rfrun adjustable preheating time t rtph 0 2500 ms range set by rtph set resistor for run feq. r rfrun 4 25 k ? set resistor for preheat feq. r rfph 4 ? k ? r rfrun parallel to r rfph set resistor for preheat time r rtph 0 25 k ? mains frequency f mains 45 65 hz notch filter operation 1) limited by maximum of current range at lvs1, lvs2 2) limited by minimum of voltage range at lvs1, lvs2 3) for higher run-frequencies the maximum load to the gate-drives must be smaller
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 44 of 55 ICB2FL02G v1.2 electrical characteristics 5.3 characteristics 5.3.1 power supply section note: the electrical characteristics involve the spread of values given within the specified supply voltage and junction temperature range t j from -25 c to 125 c. typical values represent the median values, which are related to 25 c. if not otherwise stated, a supply voltage of 15v and v hsvcc = 15v is assumed and the ic operates in active mode. furthermore, all voltages are referring to gnd if not otherwise mentioned. limit values parameter symbol min. typ. max. unit test condition vcc quiescent current1 i vccqu1 ? 90 130 a v vcc = v vccoff ? 0.5v vcc quiescent current2 i vccqu2 ? 120 160 a v vcc = v vccon ? 0.5v vcc supply current 2) i vccsupply ? 4.2 6.0 ma v pfcvs > 2.725v vcc supply current in latched fault mode i vcclatch ? 110 170 a v res = 5v lsvcc turn-on threshold lsvcc turn-off threshold lsvcc turn-on/off hyst. v vccon v vccoff v vcchys 13.6 10.0 3.2 14.1 10.6 3.6 14.6 11.0 4.0 v v v hysteresis vcc zener clamp voltage v vccclamp 15.5 16.3 16.9 v i vcc = 2ma/v res = 5v vcc zener clamp current i vcczener 2.5 ? 5 ma v vcc = 17.5v/v res = 5v high side leakage current i hsgndleak ? 0.01 2 a v hsgnd = 800v, v gnd =0v hsvcc quiescent current i hsvccqu1 1) ? 170 250 a v hsvcc = v hsvccon ? 0.5v hsvcc quiescent current 2) i hsvccqu2 1) 0.3 0.65 1.2 ma v hsvcc > v hsvccon hsvcc turn-on threshold hsvcc turn-off threshold hsvcc turn-on/off hyst. v hsvccon 1) v hsvccoff 1) v hsvcchy 1) 9.6 7.9 1.4 10.1 8.4 1.7 10.7 9.1 2.0 v v v hysteresis low side ground gnd 1) referring to high side ground (hsgnd) 2) with inactive gate
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 45 of 55 ICB2FL02G v1.2 electrical characteristics 5.3.2 pfc section 5.3.2.1 pfc current sense (pfccs) limit values parameter symbol min. typ. max. unit test condition turn ? off threshold v pfccsoff 0.95 1.0 1.05 v over current blanking + propagation delay 1) t pfccsoff 140 200 260 ns leading edge blanking t blanking 180 250 310 ns pulse width when v pfccs > 1.0v pfccs bias current i pfccsbias - 0.5 ? 0.5 a v pfccs = 1.5v 1) propagation delay = 50ns 5.3.2.2 pfc zero current detection (pfczcd) limit values parameter symbol min. typ. max. unit test condition zero crossing upper thr. 1) v pfczcdup 1.4 1.5 1.6 v zero crossing lower thr. 2) v pfczcdlow 0.4 0.5 0.6 v zero crossing hysteresis v pfczcdhys ? 1.0 ? v clamping of pos. voltages v pfczcdpclp 4.1 4.6 5.1 v i pfczcdsink = 2ma clamping of neg. voltages v pfczcdnclp - 1.7 - 1.4 - 1.0 v i pfczcdsource = - 2ma pfczcd bias current i pfczcdbias - 0.5 ? 5.0 a v pfczcd = 1.5v pfczcd bias current i pfczcdbias - 0.5 ? 0.5 a v pfczcd = 0.5v pfczcd ringing su. 3) time t ringsup 350 500 650 ns limit value for on time extension t x i zcd 500 700 900 paxs 1) turn off threshold 2) turn on threshold 3) ringing suppression time 5.3.2.3 pfc bus voltage sense (pfcvs) limit values parameter symbol min. typ. max. unit test condition trimmed reference voltage v pfcvsref 2.47 2.50 2.53 v 1.2 % overvoltage turn off (109%) v pfcvsrup 2.68 2.73 2.78 v overvoltage turn on (105%) v pfcvslow 2.57 2.63 2.68 v overvoltage hysteresis v pfcvshys 70 100 130 mv 4 % rated bus voltage under voltage (75%) v pfcvsuv 1.835 1.88 1.915 v under voltage (12.5%) v pfcvsuv 0.237 0.31 0.387 v rated bus voltage (95%) v pfcvs95 2.325 2.38 2.425 v pfcvs bias current i pfcvsbias - 1.0 ? 1.0 a v pfcvs = 2.5v
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 46 of 55 ICB2FL02G v1.2 electrical characteristics 5.3.2.4 pfc pwm generation limit values parameter symbol min. typ. max. unit test condition initial on ? time 1) t pfcon_initial ? 4.0 ? s v pfczcd = 0v max. on ? time 2) t pfcon_max 18 22.7 26 s 0.45v < v pfcvs < 2.45v switch threshold from critcm into dcm t pfcon_min 160 270 370 ns repetition time 1) t pfcrep 47 52 57 s v pfczcd = 0v off time t pfcoff 42 47 52 s 1) when missing zero crossing signal 2) at the maxima of the ac line input voltage 5.3.2.5 pfc gate drive (pfcgd) limit values parameter symbol min. typ. max. unit test condition 0.4 0.7 0.9 v i pfcgd = 5ma 0.4 0.75 1.1 v i pfcgd = 20ma pfcgd low voltage v pfcgdlow - 0.2 0.3 0.6 v i pfcgd = -20ma 10.0 11.0 11.6 v i pfcgd = -20ma 9.0 ? ? v i pfcgd = -1ma / v vcc 1) pfcgd high voltage v pfcgdhigh 8.5 ? ? v i pfcgd = -5ma / v vcc 1) pfcgd active shut down v pfcgasd 0.4 0.75 1.1 v i pfcgd = 20ma v vcc =5v pfcgd uvlo shut down v pfcgduvlo 0.3 1.0 1.5 v i pfcgd = 5ma v vcc =2v pfcgd peak source current i pfcgdsouce ? - 100 ? ma 2) + 3) pfcgd peak sink current i pfcgdsink ? 500 ? ma 2) + 3) pfcgd voltage during sink current v pfcgdhigh 11.0 11.7 12.3 v i pfcgdsinkh = 3ma pfc rise time v pfcgdrise 80 220 380 ns 2v > vlsgd > 8v 2) pfc fall time v pfcgdfall 20 45 70 ns 8v > vlsgd > 2v 2) 1) v vcc = v vccoff + 0.3v 2) r load = 4 ? and c load = 3.3nf 3) the parameter is not subject to production test ? verified by design / characterization 5.3.2.6 auxiliary (aux) limit values parameter symbol min. typ. max. unit test condition aux voltage off level v auxoff ? ? 0.24 v i aux = 1ma aux voltage on level 1 v auxon1 1.7 2.6 3.1 v i p = 0a 1) aux voltage on level 2 v auxon2 1.8 2.6 3.1 v i p = 1ma 1) aux current i aux - 0.60 -0.45 - 0.3 ma v aux = 1v / i p = 0a 1) i p = the positive current into pin zcd
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 47 of 55 ICB2FL02G v1.2 electrical characteristics 5.3.3 inverter section 5.3.3.1 low side current sense (lscs) limit values parameter symbol min. typ. max. unit test condition overcurrent shut down volt. v lscsovc1 1.5 1.6 1.7 v 1) overcurrent shut down volt . v lscsovc2 0.75 0.8 0.85 v 2) duration of overcurrent t lscsovc 450 600 700 ns capacitive mode det. level 2 v lscscap2 1.8 2.0 2.2 v during run mode capacitive mode duration 2 t lscscap2 ? 50 ? ns 3) capacitive mode det. level 3 v lscscap3 -70 -50 -27 mv capacitive mode duration 3 t lscscap3 ? 280 ? ns 4) lscs bias current i lscsbias -1.0 ? 1.0 a @ v lscs = 1.5v 1) overcurrent voltage threshold active during: start up, soft start, ignition and pre run mode 2) overcurrent voltage threshold active during: preheating and run mode 3) active during turn on of the hsgd in run mode 4) active before turn on of the hsgd in run mode
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 48 of 55 ICB2FL02G v1.2 electrical characteristics 5.3.3.2 low side ga te drive (lsgd) limit values parameter symbol min. typ. max. unit test condition 0.4 0.7 1.0 v i lsgd = 5ma 5) 0.4 0.8 1.2 v i lsgd = 20ma 5) lsgd low voltage v lsgdlow - 0.3 0.2 0.5 v i lsgd = - 20ma (source) 10.0 10.8 11.6 v 1) 9.0 ? ? v 2) lsgd high voltage v lsgdhigh 8.5 ? ? v 3) lsgd active shut down v lsgdasd 0.4 0.75 1.1 v v cc = 5v / i lsgd = 20ma 5) lsgd uvlo shut down v lsgduvlo 0.3 1.0 1.5 v v cc = 2v / i lsgd = 5ma 5) lsgd peak source current i lsgdsource ? - 50 ? ma 4) + 6) lsgd peak sink current i lsgdsink ? 300 ? ma 4) + 6) lsgd voltage during 5) v lsgdhigh ? 11.7 ? v i lsgdsinkh = 3ma lsgd rise time t lsgdrise 80 220 380 ns 2v < v lsgd < 8v 4) lsgd fall time t lsgdfall 20 35 60 ns 8v > v lsgd > 2v 4) 1) i lsgd = - 20ma source current 2) v ccoff + 0.3v and i lsgd = - 1ma source current 3) v ccoff + 0.3v and i lsgd = - 5ma source current 4) load: r load = 10 ? and c load = 1nf 5) sink current 6) the parameter is not subject to production test ? verified by design / characterization
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 49 of 55 ICB2FL02G v1.2 electrical characteristics 5.3.3.3 inverter control run (rfrun) limit values parameter symbol min. typ. max. unit test condition fixed start ? up frequency f startup 121.5 135 148.5 khz duration of soft start t softstart 9 11 13.5 ms 1) rfrun voltage in run mode v rfrun ? 2.5 ? v @ 100a 2 nd generation fl-controller for fl-ballasts preliminary datasheet page 50 of 55 ICB2FL02G v1.2 electrical characteristics 5.3.3.5 restart after lamp removal (res) limit values parameter symbol min. typ. max. unit test condition v res1 1.55 1.60 1.65 v uvlo, v cc < v ccon v res2 1.25 1.30 1.35 v high side filament in det. v res3 ? 3.2 ? v run mode i res1 - 53.2 -42.6 -32.0 a v res = 1v ; lvs1 = 5a i res2 -44.2 -35.4 -26.6 a v res = 2v ; lvs1 = 5a i res3 - 26.6 -21.3 - 16.0 a v res = 1v ; lvs1 = 30a res current source i res4 - 22.1 -17.7 -13.3 a v res = 2v ; lvs1 = 30a 5.3.3.6 lamp voltage sense (lvs1, lvs2) limit values parameter symbol min. typ. max. unit test condition source current before startup i lvssource - 5.0 - 3.0 - 2.0 a v lvs = 0v enable lamp monitoring v lvsenable1 350 530 750 mv 1) sink current for lamp det. i lvssink 8.0 12.0 18.0 a v lvs > v lvsclamp positive clamping voltage v lvsclamp ? 6.5 ? v @ i lvs = 300a ac eolcurrent threshold i lvssourceac 190 210 230 app i lvs > i lvseolpp eol 1 positive eol current thr. i lvsdcpos 34 42 50 a i lvs > i lvsdcpos eol 2 negative eol current thr. i lvsdcneg - 50 - 42 - 34 a i lvs > i lvsdcneg eol 2 1) if v lvs < v lvs1enable1 monitoring is disabled
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 51 of 55 ICB2FL02G v1.2 5.3.3.7 high side gate drive (hsgd) limit values parameter symbol min. typ. max. unit test condition 0.02 0.05 0.1 v i hsgd = 5ma (sink) 0.5 1.1 2.5 v i hsgd = 100ma (sink) hsgd low voltage v hsgdlow - 0.4 - 0.2 - 0.05 v i lsgd = - 20ma (source) 9.7 10.5 11.2 v v cchs =15v i hsgd = - 20ma (source) hsgd high voltage v hsgdhigh 7.8 ? ? v v cchsoff + 0.3v i hsgd = - 1ma (source) hsgd active shut down v hsgdasd 0.05 0.22 0.5 v v cchs = 5v i hsgd = 20ma (sink) hsgd peak source current i hsgdsource ? - 50 ? ma r load = 10 ? + c load = 1nf 1) hsgd peak sink current i hsgdsink ? 300 ? ma r load = 10 ? + c load = 1nf 1) hsgd rise time t hsgdrise 140 220 300 ns 2v < v lsgd < 8v r load = 10 ? + c load = 1nf hsgd fall time t hsgdfall 20 35 70 ns 8v > v lsgd > 2v r load = 10 ? + c load = 1nf 1) the parameter is not subject to production test ? verified by design / characterization 5.3.3.8 timer section delay timer 1 t timer1 70 100 160 ms for lamp detection delay timer 2 t timer2 74 84 94 ms for v bus > 95% inverter time t inv 100 130 160 s inverter dead time max t deadmax 1.75 2.0 2.25 s inverter dead time min t deadmin 0.8 1.05 1.3 s inverter dead time max t deadmax - 200 ? 200 ns inverter dead time min t deadmin - 200 ? 200 ns min. duration of ignition t ignition 34 40 48 ms max. duration of ignition t noignition 197 ? 236 ms duration of pre ? run t prerun 565 625 685 ms 5.3.3.9 built in customer test mode voltage at rtph pin v rtph 0 v preheating time = 0ms (skipped preheating) voltage at rtph pin v rtph 5.0 v 1) ic remains in preheating voltage at lvs1 / lvs2 pin v lvs1,2 0 v disables lamp voltage sense voltage at res pin v res 0 v disable the filament detection voltage at rfph pin v rfph 5.0 v 1) voltage at rfrun pin v rfrun 5.0 v 1) voltage at v cc pin v cc > 14.1 v voltage at res pin v res 0 v built in customer test mode - clock acceleration. decreasing time for the following procedures. preheating by factor 4 timeout ignition by factor 2 pre run by factor 15; eol by 60 1) tolerance for this voltage is: 5%; enlarged to lerance for these voltages is: -5% / +10% for a temperature range between -25c and 40c
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 52 of 55 ICB2FL02G v1.2 application example 6 application example 6.1 schematic ballast 54w t5 single lamp rfrun rfph rtph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs2 gnd 90 ... 270 vac ICB2FL02G res aux c2 c10 c11 c1 c16 c14 c13 c12 c15 c17 c19 c20 c40 r36 r1 r2 dr12 r13 r14 r15 r16 r20 r18 r21r22r23 r11 r12 r34 r35 r41 r42 r43 r26 r27 r30 r25 r45 d1...4 d9 d8 d5 d7 d6 l101 l1 l2 q1 q2 q3 lvs1 l21 l22 c21 c22 r44 figure 38: application circuit of ballast for single fluorescent lamp voltage mode preheating
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 53 of 55 ICB2FL02G v1.2 application example 6.2 bill of material 090727-1-l-54w-t5-fl2-vm bom 54w t5, single lamp, voltage mode preheat ICB2FL02G gen-2 input voltage 180vac...270v ac v_bus= 412v package package f1 fuse 1a fast wickmann typ 370 r1 470k ? .1206 fuse holder r2 470k ? .1206 k1/1 ac input r3 not assembled .1206 k1/2 ac input r4 not assembled .1206 k1/3 pe r402 not assembled .1206 k2/1 not connected r403 not assembled .1206 k2/2 high side filament k2/3 high side filament r11 470k ? .1206 k3/1 low side filament r12 470k ? .1206 k3/2 low side filament r13 33k ? .1206 k3/3 not connected r14 820k ? .1206 ic1 ICB2FL02G infineon so-20 r15 820k ? .1206 q1 spd03n60c3 infineon d-pack r16 22 ? .0805 q2 spd03n60c3 infineon d-pack r18 1 ? .1206 q3 spd03n60c3 infineon d-pack r19 not assembled .1206 q4 not assembled infineon sot-223 r20 10k ? .0805 d1?4 s1m fairchild (1000v/1a/2s) do-214ac r21 11k ? (45,5khz!) .0805 d5 murs160t3 on semi (600v/1a/75ns) smb r22 8,2k ? (106,4khz!) .0805 d6 byg26j philips (600v/1a/30ns) sod124 r23 10k ? (1000ms!) .0805 d7 byg22d philips (200v/1a/25ns) do214 r24 0,68 ? .1206 d8 byg22d philips (200v/1a/25ns) do214 r25 0,68 ? ( 0,34 ? ) .1206 d9 bzx284c16 philips sod110 r26 22 ? .1206 d10 not assembled r27 22 ? .0805 d11 not assembled r30 33 ? .1206 dr12 110k ? r34 150k ? .1206 d13 not assembled r35 150k ? .1206 d61 not assembled philips sod110 r36 56k ? .1206 l101 2x68mh/0,6a epcos b82732f2601b001 r36a 0 ? .1206 l1 pfc 1,58mh epcos 105turns/10turns efd25/13/9 r61 0 ? .1206 total gap= 1.1mm 2 pcs b78326p7373a005 t1904 l 2 1,46mh epcos 182turns efd25/13/9 total gap= 2mm 2 pcs b78326p7374a005 t1905 l 21 100h epcos b82144b1104j000 rm5 r41 68k ? .1206 l 22 100h epcos b82144b1104j000 rm5 r42 68k ? .1206 l 23 not assembled epcos b82144b1104j000 rm5 r43 68k ? .1206 c1 220nf/x2/305v epcos b32922c3224m000 rm15 r44 68k ? .1206 c2 33nf/630v/mkt epcos b32521n8333k000 rm10 r45 6,8k ? .1206 c3 3,3nf/y2-rm10 epcos b32021a3332 rm10/15 c4 220nf/x2/305v epcos b32922c3224m000 rm15 c5 not assembled epcos b32529c8102k000 rm5 c10 10f/450v epcos b43888a5106m000 single ended c11 2,2nf/50v .0805 c12 100nf/50v .0805 c13 1f/63v/mkt epcos b32529c0105k000 rm5 c14 68nf/50v epcos .0805 c15 33nf/630v/mkt epcos b32521n8333k000 rm10 c16 1nf/630v/mkt epcos b32529c8102k000 rm5 r61 0 ? .0805 c17 100nf/630v epcos b32612a6104k008 rm15 c18 not assembled rm7,5 eol1 threshold c19 22nf/50v .0805 167vpeak x 1.5=250v peak c20 4,7nf/1600v/mkp epcos b32612-j1472j008 rm15 5w c21 22nf/400v/mkt epcos b32620a4223j000 rm7,5/10 c22 22nf/400v/mkt epcos b32620a4223j000 rm7,5/10 c23 not assembled epcos b32620a4223j000 rm7,5/10 c24 not assembled epcos b32612-j1472j008 rm15 c25 not assembled roederstein rm7,5 c40 220nf/25v .0805 b-nr: 250-203 b-nr: 250-203 b-nr: 250-203 connect lvs2 (pin14) to gnd
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 54 of 55 ICB2FL02G v1.2 application example 6.3 multi lamp ballast topologies pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs 90 ... 270 vac figure 39: application circuit of ballast for two fluorescent lamps current mode preheating figure 40: application circuit of ballast for four fluorescent lamps voltage mode preheating
2 nd generation fl-controller for fl-ballasts preliminary datasheet page 55 of 55 ICB2FL02G v1.2 application example 7 package outlines figure 41 package outline with creepage distance

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